The disclosed embodiments of the present invention relate to an integrated circuit (IC) package, and more particularly, to an IC package with stress releasing structure.
Please refer to FIG. 1. FIG. 1 is a conventional IC package 100 during a reflow process. As shown in FIG. 1, the conventional IC package 100 comprises: a copper plane 102, a substrate 104, an IC chip 106, and an IC fill layer 108. As shown in FIG. 1, after the reflow process, a delamination problem happens due to a large stress between the copper plane 102, the substrate 104, and the IC chip 106, and the IC package 100 will fail due to the delamination problem.